Pipelined multi-master SDRAM controller

• Parametric configuration (size & timing).
• Zero wait-state pipelining between different masters (back2back).
• Zero wait-state pipelining between wr2wr, rd2rd, wr2rd & rd2wr bursts (back2back if same row).
• Interruptable bursts.
• Automatic refresh generation.
• Power saving mode (with self refresh).
• Soft or hard PHY.

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